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x86 SSE cvtdq2ps intruction

Posted: Sat Mar 07, 2020 5:38 pm
by steph_tsf
Is Flowstone 3.0.4 supporting the cvtdq2ps x86 SSE2 instruction?

I am talking about the ConvoRev7fixed.frm that got posted by Martin Vicanek on Wed Jun 05, 2019 11:00 pm.
http://www.dsprobotics.com/support/viewtopic.php?f=4&t=3879&start=50.
The Frequency Domain Convolution (FDM) routine appears to rely on such instruction. Such instruction converts four packed signed doubleword integers from xmm2/mem to four packed single-precision floating-point values in xmm1. Is such instruction exploited for speeding up the real/imag Frequency Domain data processing?

By the way, such ConvoRev7fixed.frm embeds a Direct Convolution (DC) routine (purely operating in time-domain thus), that's not exploiting the cvtdq2ps x86 SSE2 instruction. Has anyone tried to exploit such Direct Convolution (DC) routine, as 32-tap FIR filter? Can we push and generalize such DC routine, for it to serve as freely (statically) configurable N-tap FIR filter with N, not necessary power of two, allowed to take any value between 2 and 256? Showing as Flowstone "ready made" component? We'll deal with the impulse response generator late, as companion. Thus, within in a few weeks, Flowstone could embed a standardized "DC FIR Filter" module, along with a "DC FIR Filter Controller" that's relying on splines for drawing some arbitrary frequency response curve, and may feature a "linear phase / minimum phase" selector, and may feature a few windowing options.

Have a nice day

Re: x86 SSE cvtdq2ps intruction

Posted: Sat Mar 07, 2020 7:05 pm
by trogluddite
Yes, cvtdq2ps is supported, as well as its inverse cvtps2dq - you quite often see them paired as a fast way to round a float to the nearest integer. I only had a very brief look at the code, but it seems to be used for array/memory references (e.g. movaps xmm0, variable[eax]), where the array offset in bytes, [eax], must be in integer form.

Re: x86 SSE cvtdq2ps intruction

Posted: Sat Mar 07, 2020 9:03 pm
by steph_tsf
trogluddite wrote:Yes, cvtdq2ps is supported
Quite bizarre, under Flowstone 3.0.4, the on-the-fly assembly code text coloring appears to get paralyzed, as soon as it encounters a code line that's embedding the cvtdq2ps instruction. Is Flowstone 3.0.8 behaving the same way?

Re: x86 SSE cvtdq2ps intruction

Posted: Sat Mar 07, 2020 9:51 pm
by trogluddite
That seems very strange - those opcodes have been available since the SM days, IIRC.

Re: x86 SSE cvtdq2ps intruction

Posted: Sat Mar 07, 2020 10:12 pm
by MichaelBenjamin
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Re: x86 SSE cvtdq2ps intruction

Posted: Sun Mar 08, 2020 11:00 am
by adamszabo
steph_tsf wrote: Quite bizarre, under Flowstone 3.0.4, the on-the-fly assembly code text coloring appears to get paralyzed, as soon as it encounters a code line that's embedding the cvtdq2ps instruction. Is Flowstone 3.0.8 behaving the same way?


cvtdq2ps, its working fine here